Intel And AMD Back The Same Optical Switch

Ten nanoseconds against four hundred and fifty. That is the latency comparison Salience Labs publishes for its optical circuit switch against an electrical packet switch, and on 14 October the company closed an oversubscribed $125 million Series B on the strength of it. The round was led by Bullhound Capital. Among the new investors are AMD Ventures and Intel Capital — two corporate venture arms that are, through their parents, direct competitors in AI silicon, and that have nonetheless arrived at the same conclusion about the networking layer underneath it.

SBI Group, Hudson River Trading and the British Business Bank also came in new. Existing shareholders Applied Ventures, Oxford Science Enterprises, Cambridge Innovation Capital and Silicon Catalyst Ventures followed on. Bullhound principal Callum Stewart joins the board. The money is earmarked for deploying the switch, scaling volume manufacturing, and opening a second West Coast office in Silicon Valley.

Salience Labs was founded in 2021 on more than a decade of silicon photonics research from the University of Oxford and the University of Münster. It raised $11.5 million in 2022 and a $30 million Series A in February 2025 led by Applied Ventures and the ICM HPQC Fund, so the jump to $125 million is a fourfold step taken twenty months later — an interval that usually signals either a working demonstration or a competitive round, and in this case there is a demonstration to point at. In March the company launched a 32-port all-optical silicon photonic switch; at ECOC 2026 in Málaga in late September it ran a live 64-port version, which it called an industry first for a silicon photonics optical circuit switch. The roadmap it is now funding runs to 128 and 256 ports. Manufacturing work is being done with Tower Semiconductor, announced in February, and the test environment was built with Keysight, announced in March.

A packet switch reads a header, decides where the packet goes, and forwards it. To do that it must convert the optical signal to electrical, process it, and convert it back — and the conversion is most of the power and most of the latency. An optical circuit switch does not read anything. It establishes a physical light path from an input port to an output port and leaves it there, carrying whatever modulation format and data rate the endpoints agree on, for as long as the path is needed.

The consequences follow directly from that. Salience publishes under 10 nanoseconds of port-to-port latency, against 450 to 650 nanoseconds for an electrical switch; under 1 watt per port against about 8 watts; and data rates from 10 Gbps NRZ up to 200G, meaning 100 Gbaud PAM4. Because nothing in the path interprets the signal, the switch should in principle be indifferent to modulation format, which would mean it survives the next speed bump without being replaced — an unusual property in a data centre, where the networking layer is normally the thing that has to be ripped out first. Salience does not make that claim in those words, and the rates it publishes stop at 200G.

The cost is that a circuit switch cannot make per-packet decisions. It is useful only where traffic is predictable enough to be scheduled, and the pitch rests on the observation that AI training traffic is exactly that: collective operations with known participants, known volumes and a repeating pattern, rather than the statistical mess of general-purpose cloud workloads.

The incumbent optical circuit switch in AI data centres is based on 3D MEMS — tilting micromirrors that steer a beam from one fibre to another. The technology works, is deployed at scale, and has one structural weakness: moving a mirror takes milliseconds. On latency and power per port, Salience's own comparison table puts 3D MEMS level with its own switch; the difference it claims is in reconfiguration time, under 300 microseconds against over 1 millisecond. That is better by a factor of a few rather than by orders of magnitude, and that comparison is where the technical argument will be settled.

The distinction worth drawing is between the two things an optical switch can be asked to do. One is topology provisioning: rearranging which racks are connected to which, on timescales of seconds to minutes, as jobs come and go. Milliseconds are fine for that, and MEMS already does it. The other is dynamic scheduling inside a running job, reconfiguring the fabric between phases of a collective, which needs reconfiguration fast enough to hide inside the computation — the regime a solid-state switch is built for. Salience describes its architecture as an optical crossbar in silicon photonics, solid-state and inherently reliable, which is as much a claim about having no moving parts as about speed.

The size of the prize explains the unusual investor pairing. Salience cites Dell'Oro Group's forecast that cumulative AI back-end data centre switch spending approaches $1 trillion over 2026 to 2030, with scale-up accounting for more than half the market by 2030. Scale-up is the tightly coupled domain — the accelerators that have to behave as one machine — and it is the part of the network where latency and determinism matter most and where copper is running out of reach.

Neither AMD nor Intel makes an optical circuit switch. Both make accelerators whose utilisation depends on the fabric between them, and both are watching NVIDIA build an increasingly vertical stack in which the interconnect is not a separate purchase. An independent switch vendor that can be designed into either ecosystem is worth something to both, and worth rather more to whichever of them is further from having its own answer. AMD Ventures' Patrick Rundell framed the thesis in one line in the release: "AI infrastructure is increasingly being designed at rack scale, where networking has a direct impact on system performance."

It is also worth noting what the round is not. $125 million is a substantial sum for a photonics company and a modest one against the capital expenditure of a single AI data centre. It funds a manufacturing ramp and a port-count roadmap. It does not fund a market-share fight against an incumbent with a deployed base, and nothing in the announcement claims a design win at a named hyperscaler.

The architectural question — whether AI fabrics will be built from fast electrical packet switches or from slower-to-reconfigure optical circuit switches with packet switching pushed to the edges — has been open for several years and is not closed by a funding round. What closed on 14 October is narrower. A company with a 64-port demonstration, a foundry relationship and a test partner now has the capital to find out whether 128 and 256 ports can be built with the same insertion loss budget, and it has two of the three merchant accelerator vendors on its cap table.

For the optics industry the signal is in the component list rather than the headline. An all-optical crossbar at 256 ports is a problem in waveguide loss, crosstalk and on-chip amplification — Salience's product page describes a photonic IC that does switching and amplification on the same chip, and Intel Capital's investment note singles out its "proprietary optical amplification" — and it is a problem in fibre attach, because 256 ports means at least 512 fibres landing on a die with alignment held over temperature and time. The money raised this month is going to be spent mostly on those two things.